mail                                  register for spam free email                             
home classifieds personals entertainment career news sports shop travel
Process Engineer, Wafer Processing - San Francisco :: Jobs | Resume
           Post Your Ad For Free AVOIDING SCAMS & FRAUD ON ENTERTO           
[how to reply to this post safely?]


Process Engineer, wafer processing
Date: 2009-11-07, 8:55PM PST


RONALD KIRKISH
6440 Barron Pl, Gilroy, CA 95020
hykirkish@charter.net
______________________________________________________________________________
(408) 848-3576 Cell (408) 309-9390


SR. PROCESS ENGINEER (THIN FILM/SPUTTER/DIFFUSION)

PROCESS DEVELOPMENT * FABRICATION * PECVD * THIN FILM * SPUTTER * DIFFUSION * SEMICONDUCTOR * W-CVD * MRC * MICROMASKING * PHOTOLITHOGRAPHY * YIELD IMPROVEMENT * E-BEAM * TENCOR * VARIAN MDP SPUTTER *TiN/W-CVD * PLATINUM * Pt SILICID * MICRON TECH * NOVELLUS * METROLOGY * BACK-GRINDING * MEMS * VACUUM DEPOSITION

A Principal Thin Films Deposition Process Engineer with 15 plus yrs. experience in the semiconductor industry. Have shown demonstrable strengths in troubleshooting process issues in thin film, sputter, and diffusion, as well as Vacuum Deposition, metrology, dicing and yield enhancements. Optimized tool function, streamlined process steps, and increased throughput.

A strong mechanical and electrical knowledge of all thin film tools and support equipment and strong communication skills. Effectively trained over twenty engineers and technicians and served as company representative to vendors. Proficient in Excel, RSI, Microsoft Word, and Promis. Have had a top secret clearance (not currently active).

Sustained metal deposition manufacturing processes. Managed and qualified PECVD processes and support equipment. Conducted throughput projects, yield improvement, e-beam, and process development experiments. Maintained operation of MRC thin films sputter tools; designed and engineered deposition processes for new products. Evaluated test data and qualified process modifications. Directed production in non-standard wafer recoveries. Maintained and modified documentation.

Supervised vacuum maintenance and process technicians. Developed a means to identify problems and eliminate carbon defects related to sputter deposition, which had a major impact on increasing disk yield. Duties included thin films, sputtering, and back-grinding.

Effectively demonstrated to Integration and etch engineers that micro masking (Cu nodules left behind after plasma etching Al / 2%-Cu films) on wafers located in the mid-row of the AME etch chamber instead of the thin films area by performing a random wafer-ordered DOE across four process flows, diffusing a potentially contentious situation.

---------------------------------------------------------------------------------------------------------------------------------
SELECTED ACHIEVEMENTS AND SKILLS/ OVERVIEW/EDUCATION


Designed a new tungsten-fill process using a Novellus (Concept-1) Tool for our 0.6 Micron
Technology. Tungsten film was used for plannarization of the 1st and 2nd layer films. We had
3 film layers. In conjunction with the Tungsten film, I designed the titanium and Ti-Nitride film
layers using the MRC Star Eclipse & Endura sputter tools.

Saved over $10M in reduced scraps in 6 years by using DOE’s, data analysis, and SPC, and collaborated with engineers in photo and etch to reduce/eliminate contact and via resistance issues. Received first HERO award for development of the “Flow1” process; had a major yield impact for the company and received cash reward for applying lubrication to disc surfaces prior to test, improving yields by 45%.


RONALD KIRKISH
6440 Barron Pl, Gilroy, CA 95020
hykirkish@charter.net
______________________________________________________________________________
(408) 848-3576 Cell (408) 309-9390



Also, performed data analysis to isolate root cause of $500,000.00 lot scraps on TiW deposition wafers. Recommended change of wafer holders after a platinum run of more than 2 days which were presumed to be responsible for temperature variation, causing higher contact resistance on more sensitive metals. Received president’s check award for resolving a long standing (over ten years) yield problem.


RELAVENTCAREER OVERVIEW


• Fabtech Diodes Diffusion Engineer 09/07---11/08
• Finisar Corporation Principal Process Engineer 05/06---07/07
• Endevco Corporation Sr. Thin Film Process Engineer 08/04---04/06
• Texas Instruments Sr. Thin Film Process Engineer 1995----04/02
• StorMedia/Akashic, Sr. Sputtering Engineer 1987----1995

UNRELATED WORK 02---04
Entegris Inc. Production MGR
Mercury/Ford SALES

EDUCATION

Air Force Military Service/Had Top Secret Clearance Crypto logic Late 60’s

San Jose State University, San Jose, CA
A.A. West Valley College, Saratoga, CA Chemistry/Math
AC/DC Electronics, Digital Electronics, Mission College, Santa Clara, CA


  • it's ok to contact this poster if you are a potential employer or other principal
  • Principals only. Recruiters, please don't contact this job seeker.
  • it's NOT ok to contact this poster with services or other commercial interests
related ads | back
about uscontact us advertise with us privacy policyinvestment opportunity
© 2009 Enterto, Inc.